| 摘要 |
A semiconductor integrated circuit disclosed herein, comprises a first core which realizes a predetermined function; a second core which is different from the first core and realizes a predetermined function; a power supply circuit which is capable of supplying, to the first core, a power supply voltage different from that supplied to the second core; and a clock generating circuit which supplies a clock signal to each of the first core and the second core, the clock generating circuit including a clock skew reducing circuit which reduces clock skew occurring between the clock signal in the first core and the clock signal in the second core.
|
