| 发明名称 |
Digital line delay using a single port memory |
| 摘要 |
An apparatus for delaying video line data between a sending device and a receiving device is provided. The apparatus includes a single port random access memory ("RAM") and a processing arrangement including a first storage device coupled to the RAM and a second storage device coupled to the RAM.
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| 申请公布号 |
US2005093871(A1) |
申请公布日期 |
2005.05.05 |
| 申请号 |
US20040490015 |
申请日期 |
2004.03.18 |
| 申请人 |
FILLIMAN PAUL D.;KNOX MICHAEL D.;SIMPSON DAVID L. |
发明人 |
FILLIMAN PAUL D.;KNOX MICHAEL D.;SIMPSON DAVID L. |
| 分类号 |
H04L13/08;H04N5/04;H04N5/14;H04N5/77;H04N5/775;H04N5/781;H04N5/85;H04N5/907;H04N9/804;(IPC1-7):G06F13/00 |
主分类号 |
H04L13/08 |
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