发明名称 |
Integrated circuit structure |
摘要 |
A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate. |
申请公布号 |
US6887779(B2) |
申请公布日期 |
2005.05.03 |
申请号 |
US20030719495 |
申请日期 |
2003.11.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALCOE DAVID J.;DOWNES, JR. FRANCIS J.;JONES GERALD W.;KRESGE JOHN S.;TYTRAN-PALOMAKI CHERYL L. |
分类号 |
H01L23/498;H05K3/46;(IPC1-7):H01L21/476 |
主分类号 |
H01L23/498 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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