| 摘要 |
A clock generating circuit ( 100 ) that may prevent an erroneous clock signal from being provided to an internal logic circuit ( 105 ) has been disclosed. A clock generating circuit ( 100 ) may include a variable voltage generating circuit ( 101 ), an oscillating circuit ( 103 ), and a control circuit ( 104 ). Oscillating circuit ( 103 ) may provide an original clock signal ( 157 ). A charging circuit ( 122, 123 , and 124 ) may provide charging of a signal ( 159 ) when an original clock signal ( 157 ) achieves a predetermined amplitude. When signal ( 157 ) charges sufficiently, an oscillation stabilization signal may be provided to enable the generation of a synthesized clock signal ( 160 ). Also, at this time, a reduced voltage ( 170 ) may be provided to power an oscillating circuit ( 103 ). In this way, current consumption may be reduced and failures due to providing an erroneous clock signal to an internal logic circuit may be reduced.
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