| 摘要 |
A programmable logic device is provided which includes a multi-port RAM block with a first port including first address registers and first data registers and with a second port including second address registers and a second data registers. At least one look-up table is stored in the RAM block. First programmable logic circuitry is programmed to operate as a shift register with multiple tap outputs to multiple first address registers. Second programmable logic circuitry is programmed to operate as accumulate circuitry which includes a multi-bit input coupled to multiple first data registers and includes an accumulator output.
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