Multiple oxide thicknesses for merged memory and logic applications

摘要

Methods are provided for fabricating multiple oxide thicknesses on a single silicon wafer. Methods are provided to form multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. These methods can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Methods for forming a semiconductor device include forming a top layer of SiO₂ on a top surface of a silicon wafer. A trench layer of SiO₂ is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO₂ are such that a thickness of the top layer is different from a thickness of the trench layer.