发明名称 |
Wireless communication device with phase-locked loop oscillator |
摘要 |
A frequency generating circuit utilizes a quad modulus prescaler in which two control signals are used to select the prescaler modulus. The modulus control signals are generated by a multistage counter in which two independent counting stages are used to generate the first and second modulus control signals. The first modulus control signal is at a first logic level when the associated counter is at a non-zero value and is at a second logic level when the associated counter reaches zero. The second modulus control signal is generated by a second counter and has a first logic value when the second counter is in a non-zero state and a second logic value when the second counter reaches zero.
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申请公布号 |
US6888913(B2) |
申请公布日期 |
2005.05.03 |
申请号 |
US20020189036 |
申请日期 |
2002.07.02 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
WALKER BRETT C. |
分类号 |
H03K23/66;H03K23/68;H03L7/081;H03L7/18;H03L7/197;(IPC1-7):H03K21/00 |
主分类号 |
H03K23/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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