| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND MEMORY MODULE USING THE SAME |
| 摘要 |
INPUT/OUTPUT TERMINALS OF A FIRST SEMICONDUCTOR MEMORY DEVICE IN WHICH FAILURES OF DEFECTS EXIST IN UNITS OF MEMORY MATS (MAT0-MAT7) AND INPUT/OUTPUT TERMINALS OF A SECOND SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANT MEMORY MATS ARE CONNECTED TO ONE ANOTHER ON AN MOUNTED SUBSTRATE TO THEREBY RELIEVE THE FAILURES IN THE MEMORY MAT UNITS. A POWER SOURCE IS SUBSTANTIALLY CUT OFF FROM SUPPLYING TO A FAULTY MEMORY MAT.FIGURE 1
|
| 申请公布号 |
MY119136(A) |
申请公布日期 |
2005.04.30 |
| 申请号 |
MYPI9600285 |
申请日期 |
1996.01.25 |
| 申请人 |
HITACHI LTD.;HITACHI TOHBU SEMICONDUCTOR LIMITED |
发明人 |
KAZUMASA YANAGISAWA;KIYOSHI INOUE;MASAKAZU AOKI;MASASHI HORIGUCHI;SEIICHIRO TSUKUI;SHIGERU SUZUKI;TOSHIO SASAKI;TOSHIO SUGANO |
| 分类号 |
G11C11/413;G11C13/00;G11C11/401;G11C29/00;G11C29/04;H01L21/82;H01L21/8242;H01L27/108 |
主分类号 |
G11C11/413 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
