TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR

摘要

A trench insulated gate field effect transistor having a reduced mesa width between adjacent trenches to obtain desirable performance characteristics, in particular low Rds(on), with a suitable channel length and/or gate trench depth. The transistor has a nominal one-dimensional maximum lateral depletion width w9 at the gate-body region interface at the threshold voltage, a nominal vertical depletion length wa in the body region (4) adjacent to the drain region (2) when the design breakdown voltage Vbdss is applied between source and drain, and a nominal vertical depletion length was in the body region (4) adjacent to the source region (14), wherein the channel length I is given by I<2(Wa+ was) and the mesa width w is given by w<1 0(W9).