发明名称 |
Via electromigration improvement by changing the via bottom geometric profile |
摘要 |
An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
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申请公布号 |
US2005090097(A1) |
申请公布日期 |
2005.04.28 |
申请号 |
US20030692028 |
申请日期 |
2003.10.23 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
ZHANG BEICHAO;LOW CHUN H.;LEE HONG L.;LOONG SANG Y.;GUO GIANG |
分类号 |
H01L21/4763;H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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