发明名称 EVALUATING METHOD OF SEMICONDUCTOR WAFER
摘要 PROBLEM TO BE SOLVED: To provide the evaluating method of a semiconductor wafer capable of easily selecting an electrode pattern to form on the semiconductor wafer and capable of quickly and highly accurately evaluating electric characteristics with respect to the distribution of defects, even when they are localized in the surface of the semiconductor wafer. SOLUTION: In the evaluating method of the semiconductor wafer which is effected by evaluating the electric characteristics of an MIS type capacitor formed on the semiconductor wafer 1, a plurality of electrode patterns 12 are arranged in a reticle 11 on which the electrode patterns 12 for forming a gate electrode 3 are arranged, so that the size or the interval of arrangement of the electrode patterns 12 is different. Then the electrode patterns 12 are transferred onto the semiconductor wafer 1 to form the gate electrode 3, and manufacture the MIS capacitor while selecting a predetermined electrode pattern 12 from a plurality of electrode patterns 12 in the reticle 11 in accordance with the distribution of defects on an evaluation object or the semiconductor wafer 1. Thereafter, the electric characteristics of the MIS type capacitor are evaluated. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005116742(A) 申请公布日期 2005.04.28
申请号 JP20030348342 申请日期 2003.10.07
申请人 SHIN ETSU HANDOTAI CO LTD 发明人 OTSUKI TAKESHI
分类号 H01L21/66;(IPC1-7):H01L21/66 主分类号 H01L21/66
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