发明名称 |
Virtual reassembly system and method of operation thereof |
摘要 |
A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.
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申请公布号 |
US2005089039(A1) |
申请公布日期 |
2005.04.28 |
申请号 |
US20040993627 |
申请日期 |
2004.11.19 |
申请人 |
AGERE SYSTEMS INC. |
发明人 |
BENNETT VICTOR A.;ZSOHAR LESLIE;LAWSON SHANNON E.;MCGEE SEAN W.;SONNIER DAVID P.;KRAMER DAVID B. |
分类号 |
G06F9/30;G06F9/38;H04L12/56;H04Q11/04;(IPC1-7):H04L12/28;H04L12/54 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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