CIRCUIT DESIGN VERIFICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a circuit design verification method of a semiconductor integrated circuit capable of executing verification of driving capability in a realistic execution condition at a full-chip level to the semiconductor integrated circuit including a large-scale analog circuit. SOLUTION: This circuit design verification method comprises: an on-resistance extraction process for extracting a driver circuit for driving an internal signal node from a net list for describing all the circuits for every internal signal node to extract on-resistance in a driving path of the driver circuit for every internal signal node; a load capacity extraction process for extracting driving load capacity to be driven from the net list for every internal signal node; and a time constant extraction process for extracting the product of the driving load capacity and the on-resistance as a time constant for every internal signal node. COPYRIGHT: (C)2005,JPO&NCIPI