发明名称 DATA PROCESSOR AND DATA CONTROL UNIT
摘要 PROBLEM TO BE SOLVED: To transfer data from a plurality of devices through one bus without reducing a local transfer rate and deflecting transfer quantity among the devices. SOLUTION: A bus end state monitoring part 604 specifies which factor causes the end of a transaction of data transfer through a PCI bus 207 by a master device (any one of eight DMACs (which are not shown) built in DMA control parts 610, 611) and stores the specified result in a history storage part 620. An arbiter 606 selects an inner request for permitting the use of the PCI bus 207 on the basis of arbitration order in which priority for using the PCI bus 207 is determined for respective DMACs to be transmitting sources of the received inner request, reservation requests and the history of end factors of respective transactions informed from the bus end state monitoring part 604. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005115464(A) 申请公布日期 2005.04.28
申请号 JP20030345836 申请日期 2003.10.03
申请人 FUJI XEROX CO LTD 发明人 SAKAMOTO TAKASHI
分类号 G06F13/362;(IPC1-7):G06F13/362 主分类号 G06F13/362
代理机构 代理人
主权项
地址