发明名称 |
MASTER LATCH CIRCUIT WITH SIGNAL LEVEL DISPLACEMENT FOR A DYNAMIC FLIP-FLOP |
摘要 |
A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK), resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) and which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (ClkDELAY) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage . |
申请公布号 |
WO2005039050(A2) |
申请公布日期 |
2005.04.28 |
申请号 |
WO2004EP09853 |
申请日期 |
2004.09.03 |
申请人 |
INFINEON TECHNOLOGIES AG;BERTHOLD, JOERG;GEORGAKOS, GEORG;HENZLER, STEPHAN;SCHMITT-LANDSIEDEL, DORIS |
发明人 |
BERTHOLD, JOERG;GEORGAKOS, GEORG;HENZLER, STEPHAN;SCHMITT-LANDSIEDEL, DORIS |
分类号 |
H03K3/037;H03K3/356 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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