发明名称 OUTPUT SIGNAL HIGH-SPEED DECODING METHOD AND APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a means for realizing high-speed maximum likelihood decoding processing. SOLUTION: An input signal is divided into blocks by a signal distributor (103), and successively supplied to one of a plurality of maximum likelihood decoders (104). In each decoder, the input signal is stored in a buffer storage device (106), decoding processing is performed at a low speed, and results are outputted in parallel from the buffer storage devices (108). A maximum likelihood decoder of the required operating speed is provided by low-speed circuit technology. Further, centralized control of serial/parallel conversion is made within the decoder, thereby supplying results of processing in parallel at a low speed to signal processing apparatuses, after decoding processing. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005117674(A) 申请公布日期 2005.04.28
申请号 JP20040320037 申请日期 2004.11.04
申请人 HITACHI LTD 发明人 SAWAGUCHI HIDEKI
分类号 G06F11/10;G11B20/10;G11B20/18;H03M13/41;H04L1/00;(IPC1-7):H03M13/41 主分类号 G06F11/10
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