发明名称 |
Chip scale package and method of fabricating the same |
摘要 |
Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises conductive layers with a designated depth formed on an upper and a lower surfaces of a chip, and electrode surfaces formed on the same side surfaces of the conductive layers, which are connected to corresponding connection pads of a printed circuit board. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.
|
申请公布号 |
US2005087848(A1) |
申请公布日期 |
2005.04.28 |
申请号 |
US20040988523 |
申请日期 |
2004.11.16 |
申请人 |
SAMSUNG ELECTRO-MECHANICS CO., LTD. |
发明人 |
YOON JOON H.;CHOI YONG C.;BAE SUK S. |
分类号 |
H01L23/12;H01L21/60;H01L21/78;H01L23/31;H01L23/48;H01L23/485;H05K3/34;H05K5/00;(IPC1-7):H01L21/48;H01L29/40 |
主分类号 |
H01L23/12 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|