发明名称 |
System and method for controlling a multiplexer for selecting between an input clock and an input duty-cycle-corrected clock and outputting the selected clock and an enable signal |
摘要 |
A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
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申请公布号 |
US6886106(B2) |
申请公布日期 |
2005.04.26 |
申请号 |
US20010978358 |
申请日期 |
2001.10.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BROCK BISHOP CHAPMAN;CARPENTER GARY DALE;CASWELL AMANDA CHRISTINE;MACDONALD ERIC WILLIAM;RUBIDOUX TIMOTHY JOE |
分类号 |
G06F1/08;(IPC1-7):G06F1/04;G06F1/32;H03K3/017 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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