Digitally-switched impedance with multiple-stage segmented string architecture

摘要

A multiple-stage digitally-switched impedance has one "type B" stage and at least two "type A" stages. The type A stages are cascaded between high and low reference nodes and the type B stage. Each stage comprises a string of series-connected impedances and a switch network. A decoder responds to an digital input signal by controlling the switch networks to switch selectable portions of the strings in the type A stages into a series connection with the type B stage's string, and to control the type B stage's switch network to tap its string at a location to provide a impedance corresponding to the n-bit digital input signal between the final output node and at least one of the high and low reference nodes. Each stage provides a portion of the impedance's n-bit resolution, and the sum of the bits of resolution provided by each stage equals the total n-bit resolution.