发明名称 Design method for multilayer wiring board
摘要 A method of routing in a multilayer wiring board, such as a built-up wiring board, which is interconnected by via holes between only adjacent layers includes steps of reading a parameter for each kind of built-up via of a multilayer wiring board, and setting a via hole size, shift direction, and via pitch of each layer. The information of the read parameter is stored in a memory. In a routing step, wirings of the multilayer wiring board having a built-up via is designed based on the information of the parameter stored in the memory in the parameter reading step, and an instruction for a start layer and a last layer.
申请公布号 US6886151(B2) 申请公布日期 2005.04.26
申请号 US20020150961 申请日期 2002.05.21
申请人 NEC CORPORATION 发明人 TANAKA SHINJI
分类号 G06F17/50;H05K3/00;H05K3/46;(IPC1-7):G06F17/50 主分类号 G06F17/50
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