| 摘要 |
PROBLEM TO BE SOLVED: To provide a wiring treatment method of a semiconductor integrated circuit, in which treatment is carried out so that actual wiring of a path having high possibility that violation of timing limitation will occur has a value approximated to wiring length estimated in virtual wiring. SOLUTION: Virtual wiring is formed between function blocks based on layout data by a floor plan of the semiconductor integrated circuit. Timing analysis is performed based on information on wiring capacity and resistance, which are obtained from virtual wiring. Wiring of the path where margin with respect to timing limitation is less than a threshold which is previously set is detected based on timing information, and it is set to be an object of preferential wiring. An actual wiring treatment is performed so that wiring being the object of preferential wiring becomes less than the threshold on a difference of wiring length between actual wiring and virtual wiring. Thus, a remarkable increase of delay with respect to an estimate for virtual wiring can be prevented, and occurrence of unexpected timing limitation violation after detailed wiring can be reduced. COPYRIGHT: (C)2005,JPO&NCIPI
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