INSTRUCTION ENCODING FOR VLIW PROCESSORS

摘要

Data processing systems, for example VLIW processors, comprise a register file (RF0, RF1) for storing data, and a number of issue slots (IS0 - IS5), wherein each issue slot has at least one execution unit. The data processing system processes the data stored in the register file, under control of instruction words. Especially in case of a large number of issue slots, it is not always possible to issue an instruction to each issue slot. Therefore the instruction words are often compressed to save instruction memory. A disadvantage is that decoding these compressed instruction words requires complex logic. According to the invention, a first instruction word (IW1) and a second instruction word (IW2) are used. The first instruction word corresponds to a first instruction set, wherein the first instruction word encodes a plurality of instructions to be executed in parallel by the plurality of issue slots. The second instruction word corresponds to a second instruction set, wherein the second instruction word encodes at least one instruction to be executed by a single issue slot. As a result, instructions can be encoded more efficiently. The decoding of the first instruction word becomes faster, since less shifting during decoding is required. The decoding of the second instruction word is achieved with a relatively simple and fast decoder.