AUTOMATED DESIGN METHOD AND DEVICE, RETICLE SET, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DESIGN PROGRAM

摘要

PROBLEM TO BE SOLVED: To make useable a wiring grid adjoining a wiring while forming a plurality of via plugs in an expansion region, in a semiconductor integrated circuit.

SOLUTION: The semiconductor integrated circuit comprises a lower wiring layer composed of a lower layer line pattern 40iincluding a conductive film extending in the lower layer preference direction and of a lower layer expansion region 42 including a conductive film extending in the direction different from the lower layer preference direction from the terminal part of the lower layer line pattern 40iso that a dimension W2 measured in the lower layer reference direction is wider than a line width W1 of the lower layer line pattern 40i; an interlayer insulating film disposed on the lower wiring layer; a plurality of via plugs composed of a conductor in which a plurality of via holes 41a, 41b formed in the interlayer insulating film are embedded and which connects its bottom to a lower layer expansion region 42 arrayed in the direction where the lower layer expansion region 42 extends; and an upper wiring layer disposed on the interlayer insulating film and comprising an upper layer line pattern 60jcomposed of a conductive film extending in the direction where the lower layer expansion region 42 extends as the position connected to the top of the plurality of wire plugs as a terminal part.

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