发明名称 WAFER-LEVEL PACKAGE AND ITS MANUFACTURING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a thin-type wafer-level package of a chip size which is suitable for a thin film device and a high-frequency device, using MEMS technique or the like and has a cavity the inside, and to provide its manufacturing method. <P>SOLUTION: Inner electrode pads 13, 23 and a conductive bump 24 to a device 12 are formed in at least one of two substrates 11, 21. An inner electrode pad is formed in any one of the two substrates, and a bonding resin 25 is applied to a circumference thereof. Both the substrates are made to face, and the inner electrode pad is connected by means of the conductive bump, and are laminated by the bonding resin and sealed. A well 26, reaching the inner electrode pad is formed from the rear surface of any one of the two substrates, an outer electrode 27 is formed in the inner surface of the well and the rear surface of an insulator substrate simultaneously, and a chip is separated by dicing. In this way, a wafer-level package is prepared. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005109221(A) 申请公布日期 2005.04.21
申请号 JP20030341982 申请日期 2003.09.30
申请人 TOSHIBA CORP 发明人 KAWAKUBO TAKASHI;YASUMOTO YASUAKI;ITAYA KAZUHIKO
分类号 H01L23/12;H01L21/48;H01L21/60;H01L23/055;H01L23/14;H01L23/498;H01L25/065;H01L25/07;H01L25/18;H03H3/02;H03H9/02;H03H9/10;H03H9/17 主分类号 H01L23/12
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