| 摘要 |
PROBLEM TO BE SOLVED: To provide a 3D (3-dimensional) integrating method of manufacturing 3D integrated circuit, in which a pFET is arranged on a crystal surface optimal for this device, and an nFET can be arranged on a crystal surface optimal for this type of device. SOLUTION: In a first 3D integrating method, a first semiconductor device is constituted on a semiconductor surface of a first SOI (silicon-on-insulator) substrate, in advance, and a second semiconductor device is constituted on a semiconductor surface of a second SOI substrate in advance. After these two structures have been constituted in advance, these structures are combined mutually, and they are interconnected via a wafer, namely, via a penetration via hole. In a second 3D integrating method, the first semiconductor device is formed, in such a way that a blanket SOI substrate having a first SOI layer of a first crystal orientation is combined at a surface of the wafer, which has been manufactured, in advance and has the second semiconductor device, on a second SOI layer having a crystal orientation different from that of the first SOI layer and the first semiconductor device on the first SOI layer. COPYRIGHT: (C)2005,JPO&NCIPI
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