发明名称 |
Method of extracting properties of back end of line (BEOL) chip architecture |
摘要 |
A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.
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申请公布号 |
US2005086628(A1) |
申请公布日期 |
2005.04.21 |
申请号 |
US20030687475 |
申请日期 |
2003.10.16 |
申请人 |
FILIPPI RONALD G.JR.;FIORENZA GIOVANNI;LIU XIAO H.;MURRAY CONAL E.;NORTHROP GREGORY A.;SHAW THOMAS M.;WACHNIK RICHARD A.;WISNIEWSKI MARY YVONNE L. |
发明人 |
FILIPPI RONALD G.JR.;FIORENZA GIOVANNI;LIU XIAO H.;MURRAY CONAL E.;NORTHROP GREGORY A.;SHAW THOMAS M.;WACHNIK RICHARD A.;WISNIEWSKI MARY YVONNE L. |
分类号 |
G06F17/50;G06F19/00;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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