| 摘要 |
A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.
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