发明名称 PLL FREQUENCY SYNTHESIZER
摘要 <P>PROBLEM TO BE SOLVED: To enhance neighboring C/N, to shorten lockup time and to reduce residual FM. <P>SOLUTION: A phase comparator 101 compares the phase between a signal inputted from an input end I1 and a signal outputted from a frequency divider, and a current signal corresponding to the phase difference is converted into a voltage signal by a plurality of loop filters 103 or 104 having a different cut-off frequency and outputted to a voltage controlled oscillator 106. The voltage controlled oscillator 106 oscillates a frequency signal corresponding to an inputted voltage signal. The oscillation signal is branched at a branch point P1 and outputted to a frequency divider 107 and an output end O1. A variable capacity capacitor 108 is connected with a branch point P2 branched further on the post-stage of the branch point P1, and a control circuit 109 interlocked with switching control of a loop filter controls the capacity. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005109608(A) 申请公布日期 2005.04.21
申请号 JP20030336800 申请日期 2003.09.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SASAKI AKIRA
分类号 H03L7/093;H03L7/107;H03L7/18 主分类号 H03L7/093
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