发明名称 VIA CHECK STRUCTURE
摘要 PROBLEM TO BE SOLVED: To subject an uppermost interconnect line to a potential contrast method so as to check faults in the vias of all layers and to pinpoint layers and spots where defective vias are located even in a three or more-layered wiring structure. SOLUTION: A via check structure consists of lower interconnect lines (first interconnect line 21 and a second interconnect line 22) which are connected in the shape of chains through a first via 31 and laid running through a board, and of a plurality of upper interconnect lines (third interconnect line to fifth interconnect line) 23 to 25 which are electrically connected to the lower interconnect lines 21 and 22 through the vias (second via 32 to fourth via 34) while branching out. The potential contrast images of the uppermost interconnect lines 25 are changed corresponding to the layers where defective vias are located, so that all layers and spots where defective vias are located can be pinpointed on the basis of the potential contrast image. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005108913(A) 申请公布日期 2005.04.21
申请号 JP20030336733 申请日期 2003.09.29
申请人 NEC YAMAGATA LTD 发明人 SATO HIROSHI
分类号 H01L21/66;(IPC1-7):H01L21/66 主分类号 H01L21/66
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