发明名称 Multi-chip module and method for testing
摘要 A multi-chip module having an integrated semiconductor mass memory and a logic chip is disclosed. In accordance with one aspect of the invention, the integrated logic chip includes electrically programmable links or other non-volatile memory for permanently storing memory cells of the memory chip identified as defective. In the event of accesses to the memory chip the address present is compared with the stored addresses of the defective cells by a comparator and, if appropriate, a changeover is made from the memory chip to a volatile memory provided for this purpose in the logic chip, in which redundant memory cells are formed. The result is a significantly increased yield and a reduced test complexity, particularly in mass production.
申请公布号 US2005086564(A1) 申请公布日期 2005.04.21
申请号 US20040924565 申请日期 2004.08.24
申请人 FRANKOWSKY GERD;OSSIMITZ PETER 发明人 FRANKOWSKY GERD;OSSIMITZ PETER
分类号 G01R31/3185;G11C29/00;H01L23/02;(IPC1-7):H01L23/02 主分类号 G01R31/3185
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