发明名称 Trench MIS device with reduced gate-to-drain capacitance
摘要 Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.
申请公布号 US6882000(B2) 申请公布日期 2005.04.19
申请号 US20010927320 申请日期 2001.08.10
申请人 SILICONIX INCORPORATED 发明人 DARWISH MOHAMED N.;GILES FREDERICK P.;LUI KAM HONG;CHEN KUO-IN;TERRILL KYLE
分类号 H01L21/336;H01L29/08;H01L29/423;H01L29/739;H01L29/78;(IPC1-7):H01L27/108;H01L29/76;H01L29/94;H01L31/119 主分类号 H01L21/336
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