发明名称 Inter-block interface circuit and system LSI
摘要 An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuits 112 and 114 are respectively provided in blocks 102 and 104 that communicate signals with one another, and interface control circuit 202 dynamically controls respective input levels of gate circuits 112 and 114 . In other words, the circuit 202 fixes an input level of gate circuit 112 or 114 in a block whose power supply is ON to "L", and thereby compulsively fixes an output level of the gate circuit to "L".
申请公布号 US6882175(B2) 申请公布日期 2005.04.19
申请号 US20030460175 申请日期 2003.06.13
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 MOTEGI ISAO;NAGATA EIJI
分类号 H01L21/822;H01L27/04;H03K19/00;(IPC1-7):H03K17/16;H03K19/003 主分类号 H01L21/822
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