发明名称 Minimization of microelectronic interconnect thickness variations
摘要 An efficient TCAD tool to analyze the variation of topography and thickness of interconnects and components of integrated circuits introduced by multiple-layer chemical-mechanical planarization (CMP). Contact stress distribution is determined on all scales as a function of topography. A formulation is used relating the pad deformation and therefore stress directly to pattern topography ({d}), and the pad mechanical properties. The 3-dimensional stress and deformation field is described, along with representation of the statistical pad roughness and slurry thickness information. These process conditions are also functions of the surface topography and contact regimes. The stress-topography relationship is represented as [A]{P}={d}, where [A] is the influence coefficient matrix determined by the contact mechanics, and {P} and {d} represent local stress and topography on patterns. With given initial topography and slurry rate kinetics, the surface evolution at each time step of CMP can be traced iteratively to obtain post-CMP topography.
申请公布号 US6883153(B2) 申请公布日期 2005.04.19
申请号 US20030340534 申请日期 2003.01.10
申请人 INTEL CORPORATION 发明人 JIANG LEI;SHANKAR SADASIVAN
分类号 G06F17/10;G06F17/50;G06F19/00;H01L21/768;(IPC1-7):G06F17/50 主分类号 G06F17/10
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