| 发明名称 |
Semiconductor device that include silicide layers |
| 摘要 |
There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
|
| 申请公布号 |
US6882018(B2) |
申请公布日期 |
2005.04.19 |
| 申请号 |
US20030703632 |
申请日期 |
2003.11.10 |
| 申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
OHTANI HISASHI;FUJIMOTO ETSUKO |
| 分类号 |
H01L29/78;H01L21/336;H01L21/77;H01L21/84;H01L27/12;H01L29/45;H01L29/786;(IPC1-7):H01L29/76 |
主分类号 |
H01L29/78 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
