发明名称 Method and system for generating a circuit design including a peripheral component connected to a bus
摘要 Method and system for generating an electronic circuit design. A first logic block is instantiated in the design in response to user input controls. The first logic block includes parameters that specify its interface requirements. Bus interface blocks, which are parameterizable to connect a logic block to a bus, are provided in a library. Bus interface blocks that connect the first logic block to the bus are instantiated in the design, and the bus interface blocks are parameterized in response to the requirements of, the first logic block. The bus interface blocks are connected to the first logic block in such a way that the first logic block is extended into a peripheral that can communicate with the bus.
申请公布号 US6883147(B1) 申请公布日期 2005.04.19
申请号 US20020304471 申请日期 2002.11.25
申请人 XILINX, INC. 发明人 BALLAGH JONATHAN B.;MILNE ROGER BRENT;STROOMER JEFFREY D.;KELLER ERIC R.;HWANG L. JAMES;JAMES-ROXBY PHILIP B.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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