发明名称 |
Memory cell array with staggered local inter-connect structure |
摘要 |
A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.
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申请公布号 |
US2005077567(A1) |
申请公布日期 |
2005.04.14 |
申请号 |
US20030685044 |
申请日期 |
2003.10.14 |
申请人 |
RANDOLPH MARK W.;HADDAD SAMEER S.;THURGATE TIMOTHY;FASTOW RICHARD |
发明人 |
RANDOLPH MARK W.;HADDAD SAMEER S.;THURGATE TIMOTHY;FASTOW RICHARD |
分类号 |
G11C16/04;H01L21/8246;H01L21/8247;H01L27/115;(IPC1-7):H01L29/788 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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