| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of accessing data in a memory cell array at a high speed in synchronism with an external system clock. SOLUTION: The semiconductor memory to which an external clock is inputted is provided with: a plurality of memory banks operated at an active cycle indicating a read or write cycle, or a precharge cycle; a means for latching the logical level of an inputted row address strobe signal in response to the rising or falling edge of the external clock; an external address input means for selecting one of the memory banks; and a means for receiving the latched logical level and an address from the address input means, and outputting, when the logical level is at a first logical level, an activating signal to the selected memory bank to operate it at the active cycle, and outputting a nonactivating signal to the unselected memory bank to operate it at the precharge cycle. COPYRIGHT: (C)2005,JPO&NCIPI
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