发明名称 Image processing device
摘要 An inexpensive and simple circuit for improving the quality of a dynamic image, with appropriate, flexible dynamic image qualities processing, even with plural input signal sources. A memory unit has a region for storing images of at least one screen, and a memory control unit for writing image data to the memory unit on the basis of a first clock and a first image synchronizing signal and for outputting image data read out from the memory unit on the basis of a second clock and a second image synchronizing signal. A clock generating unit provides the second clock, and a synchronizing control unit inputs the second clock and outputs the second image synchronizing signal. The synchronizing control unit generates one signal asynchronous to the first image synchronizing signal, by dividing the second clock, and another that is and synchronized with the first synchronizing signal, by using the second clock, and selects one of the signals it has produced to be output as the second image synchronizing signal. In a case of multiple input signals, then such fourth image synchronizing signals equal in number to the input signals are produced.
申请公布号 US2005078101(A1) 申请公布日期 2005.04.14
申请号 US20040948343 申请日期 2004.09.24
申请人 CANON KABUSHIKI KAISHA 发明人 SHIGETA KAZUYUKI
分类号 G09G3/36;G09G3/28;G09G5/00;H04L12/40;H04L12/64;H04N5/20;H04N5/202;H04N5/45;H04N5/66;(IPC1-7):G09G5/00 主分类号 G09G3/36
代理机构 代理人
主权项
地址