| 摘要 |
A circuit and method of generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases: generating a set of m bits, wherein m is an integer, of a first symbol and a set of m bits of a second symbol from a first set of data during a first clock phase; and generating a set of n bits, wherein n is an integer, of the first symbol and a set of n bits of the second symbol from a second set of data during a second clock phase. |
