| 摘要 |
<P>PROBLEM TO BE SOLVED: To establish synchronization of a frame phase of packet signals converted in parallel even when a high speed packet signal is converted into many parallel signals particularly and consecutive packet signals each having the number of bits less than the number of parallel signals are processed. <P>SOLUTION: A frame phase synchronizing circuit is provided with: at least two or more shift register sections for shifting bits of the packet signals converted in parallel; an FCS arithmetic section for applying an FCS arithmetic operation of an FCS region of the packet signals to between the parallel packet signals outputted from at least two or more of the shift register sections; a phase difference discrimination section for discriminating a frame phase difference of the parallel packet signals on the basis of a result of the FCS arithmetic operation of the FCS arithmetic section; and a phase difference absorbing section for absorbing the frame phase difference by selecting the parallel signals whose frame phases are matched with each other from the parallel packet signals whose bits are shifted by at least two or more of the shift register sections on the basis of a result of the phase difference discrimination section. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
