| 摘要 |
PROBLEM TO BE SOLVED: To effectively control gate dimensions in a semiconductor device during etching wherein both N-type polysilicon gate and P-type polysilicon gate are arranged simultaneously. SOLUTION: During the simultaneous etching of the both gates in a semiconductor device wherein an N-type polysilicon gate and a P-type polysilicon gate are arranged, the area of undoped silicon gates which are dummy electrodes is arranged to be larger than the total area of the N-type and P-type doped polysilicon gates, so that the undoped polysilicon is dominant over the doped polysilicon during dry etching for the polysilicon gates. COPYRIGHT: (C)2005,JPO&NCIPI
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