| 摘要 |
PROBLEM TO BE SOLVED: To provide a delayed phase-locked loop circuit and communication apparatus using the same in which a normal clock signal can be generated even in a mis-lock state. SOLUTION: In the delayed phase-locked loop circuit comprising: a phase comparator 3 that compares a phase of a reference frequency signalΦ0 to that of a feedback signalΦfb and outputs an error signal corresponding to a difference therebetween; delay time control means 4, 5 that form a delay time control signal based on the error signal; and a voltage controlled delay means 7 to which the reference frequency signal is inputted, and which includes a plurality of voltage controlled delay elements DE1-DE5 for delaying the reference frequency signal just for a delay time controlled by the delay time control signal and outputs a delay signal of the final stage to the phase comparator 3 as the feedback signal, in the voltage controlled delay means 7, the number of voltage controlled delay elements is selected to a prime number in such a manner as to distribute a rise of a delay signal outputted from each voltage controlled delay element. COPYRIGHT: (C)2005,JPO&NCIPI
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