发明名称 Chip package with degassing holes
摘要 A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.
申请公布号 US2005077077(A1) 申请公布日期 2005.04.14
申请号 US20040000255 申请日期 2004.11.30
申请人 INTEL CORPORATION 发明人 WOOD DUSTIN P.
分类号 H01L23/498;H05K1/02;H05K1/11;H05K3/46;(IPC1-7):H01B17/20 主分类号 H01L23/498
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