发明名称 Data transmission system for linking digital signal processors has common databus and respective clock signal line between master digital signal processor and each slave digital signal processor
摘要 <p>The data transmission system (1) has a master digital signal processor (2) transmitting a data signal to at least one of a number of slave digital signal processors (7,10,13) via at least one databus (19), a clock signal transmitted to the selected slave digital signal processor in synchronism with the data signal, via a respective clock signal line (16,17,18) between the master digital signal processor and the slave digital signal processor and used for addressing the required slave digital signal processor. Also included are Independent claims for the following: (a) a digital signal processor; (b) a method for transmission of data signals between a master digital signal processor and a number of slave digital signal processors.</p>
申请公布号 DE10345256(B3) 申请公布日期 2005.04.14
申请号 DE2003145256 申请日期 2003.09.29
申请人 INFINEON TECHNOLOGIES AG 发明人 LUEFTNER, THOMAS
分类号 G06F13/42;(IPC1-7):H04L12/403 主分类号 G06F13/42
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