发明名称 Wire delay distributed model
摘要 An improved method of using the Elmore Model to estimate the delay which is associated with the a clock buffer output. The improved method provides that the clock buffer output resistor is taken into account when the Elmore Model is used to calculate the delay. Also provided is a method of using the Elmore Model to estimate wire delay, where the method includes steps of calculating an approximate delay based on a distributed RC model, and using a capacitance value corresponding to the approximate delay in the Elmore Model to estimate the wire delay.
申请公布号 US6880141(B1) 申请公布日期 2005.04.12
申请号 US20010827434 申请日期 2001.04.06
申请人 LSI LOGIC CORPORATION 发明人 TETELBAUM ALEXANDER
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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