发明名称 PROCESSOR AND INTERRUPT CONTROL METHOD FOR THE SAME
摘要 PROBLEM TO BE SOLVED: To execute safe interrupt handling in a processor highly responsively. SOLUTION: Upon an external interrupt during the processing of a vector instruction, the processor 1 holds external interrupt handling until finishing the vector instruction processing. The external interrupt handling is executed after the vector instruction processing in progress is finished. This can prevent the situation wherein interrupt handling causes incorrect values of a vector instruction computation result to enable the safe execution of interrupt handling. A vector instruction execution detection part 109 implemented as hardware in the processor 1 detects whether a vector instruction is processed or not, and according to the detection result, the execution of interrupt handling is controlled. This can provide higher processing responsiveness than the software control of interrupt handling. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005092467(A) 申请公布日期 2005.04.07
申请号 JP20030323783 申请日期 2003.09.16
申请人 SEIKO EPSON CORP 发明人 TODOROKI MITSUNARI
分类号 G06F9/48;G06F9/46;(IPC1-7):G06F9/46 主分类号 G06F9/48
代理机构 代理人
主权项
地址