发明名称 |
Maximum likelihood bit synchronizer and data detector |
摘要 |
A bit synchronizer (16) that includes a tapped delay line (38) connected to a plurality of timing hypothesis circuits. A control and adjudication circuit (50) is connected to the timing hypothesis circuits, and compares outputs of the timing hypothesis circuits and selects one. Each of the timing hypothesis circuits includes a sum-and-dump summer (112) that is connected to outputs of the tapped delay line (38). The timing hypothesis circuits further include an absolute value circuit (46) and an averaging circuit (48). A select switch (60) is connected to the summers (112) and receives a switch control signal from the control and adjudication circuit (50). A threshold test circuit (62) compares the selected output signal to a threshold value and outputs a mark or space symbol.
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申请公布号 |
US2005074078(A1) |
申请公布日期 |
2005.04.07 |
申请号 |
US20030676525 |
申请日期 |
2003.10.01 |
申请人 |
NORTHROP GRUMMAN CORPORATION |
发明人 |
PAWLOWSKI PETER R.;RICHES MARK A. |
分类号 |
H04L7/033;H04L27/06;(IPC1-7):H04L27/06 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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