| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a digital signal processing apparatus for controlling a frequency of a clock signal in a receiver side apparatus in compliance with a residual capacity of a buffer memory. <P>SOLUTION: A buffer memory 2 for storing a digital signal is provided to an output side of a reception section 1, and a D/A converter 3 and an output apparatus 4 are sequentially connected to the output side of the buffer memory 2. A PLL circuit 5 is connected to the buffer memory 2 and the D/A converter 3. A clock signal from the PLL circuit 5 is used for a reference clock used when reading the buffer memory 2 and for analog conversion of the D/A converter 3. A residual monitor section 6 is provided to the buffer memory 2 and a frequency control section 7 for setting the frequency of the clock signal generated by the PLL circuit 5 is connected to the residual capacity monitor section 6. The residual capacity monitor section 6 turns on/off a half flag HF by using a half of the storage capacity of the buffer memory for a threshold. The frequency control section 7 detects ON/OFF of the half flag HF to output a frequency increasing/decreasing command to the PLL circuit 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
