发明名称 COMMUNICATION CONTROLLER AND INFORMATION PROCESSOR
摘要 PROBLEM TO BE SOLVED: To prevent the reception of data in the communication setting which is different from the communication setting of an information processor. SOLUTION: The received frame data are delayed during Toct in a Toct data delaying shift register circuit 72. A frame data collation determination circuit 75 determines whether the communication setting of the data outputted from the Toct data delaying shift register circuit 72 is coincided with the communication setting of its own device. When the communication setting is not coincided with each other, the data held in the Toct data delaying shift register circuits 72 are cleared and the received frame data are not outputted to a data reception control unit 32. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005094483(A) 申请公布日期 2005.04.07
申请号 JP20030326394 申请日期 2003.09.18
申请人 FUJI ELECTRIC SYSTEMS CO LTD 发明人 OTA HIDEKI;KATSUNO TORU
分类号 H04L29/06;(IPC1-7):H04L29/06 主分类号 H04L29/06
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