| 摘要 |
PROBLEM TO BE SOLVED: To execute accurate timing design by applying not any uniform delay coefficients but delay coefficients corresponding to the characteristics of each clock path to a branched clock line. SOLUTION: At first, a net list 101 is inputted, and the maximum and minimum values of delay coefficients corresponding to the characteristics of respective clock paths at a data transmission side FF and a data reception side FF are set by a path-categorized delay coefficient setting process 104, and a timing analysis process 106 is executed. Then, a circuit to be inserted is assumed by an insertion circuit assuming circuit 108 by referring to the timing analysis result 107, and time to be generated by the circuit to be inserted is estimated by an insertion delay estimating process 110, and the insertion circuit for eliminating any timing error is selected by an insertion circuit deciding process 112. COPYRIGHT: (C)2005,JPO&NCIPI
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